Computation Sharing Programmable FIR Filter Using Canonic Signed Digit Representation

This paper presents a low-cost and highperformance programmable digital finite impulse response (FIR) filter. The architecture employs the computation sharing algorithm to reduce the computation complexity. In the traditional computation sharing algorithm, critical path constraint on the output summation stage is a bottleneck, thus, the canonic-sign-digit representation is utilized for filter coefficients to relax the timing constraints. Due to the relaxation of critical path timing, more computation cost is reduced. Thus, the goal of low-cost and high-performance can be achieved. The synthesis results show that the proposed architecture has more area cost reduction for larger tap length compared with the traditional computation sharing FIR filter .